衬底偏置条件下SOI纳米线MOS晶体管的后通道迁移率提取

F. Bergamaschi, G. Wirth, S. Barraud, M. Cassé, M. Vinet, O. Faynot, M. Pavanello
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引用次数: 0

摘要

在这项工作中,通过分离背道中电子的迁移率来分析SOI纳米线MOS晶体管的有效迁移率,这是当衬底偏压施加时产生的。测量是在具有Ω-gate结构和可变通道长度的n型器件中完成的。较长和较短的沟道器件在后沟道中都表现出较高的迁移率,但随着衬底偏置的增加,迁移率明显降低,在强后偏置水平下达到接近前沟道的值。这种效应与外加的栅极电压无关。三维TCAD仿真验证了分离后通道迁移率的方法,表明前通道迁移率不随衬底偏压的增加而改变。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing
In this work, an analysis of the effective mobility of SOI nanowire MOS transistors is performed by separating the mobility of electrons in the back channel, which is created when substrate bias is applied. Measurements are done in n-type devices with an Ω-gate structure and variable channel length. Both longer and shorter channel devices present higher mobility in the back channel, but strong mobility reduction is observed with the increase of the substrate bias, reaching values close to that of the front channel at strong back bias levels. This effect is independent of the applied gate voltage overdrive. Three-dimensional TCAD simulation validates the method used to separate the back channel mobility, showing that the front channel mobility is not changed by the increase in substrate bias.
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