Xiaoling Li, Yuxiang Chen, Yuheng Wu, Hao Chen, W. Weber, Adel Nasiri, R. Cuzner, Yue Zhao, A. Mantooth
{"title":"低寄生和兼容系统接口的高电压SiC功率模块","authors":"Xiaoling Li, Yuxiang Chen, Yuheng Wu, Hao Chen, W. Weber, Adel Nasiri, R. Cuzner, Yue Zhao, A. Mantooth","doi":"10.1109/APEC43599.2022.9773726","DOIUrl":null,"url":null,"abstract":"SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are strong candidates to replace Si devices in high voltage applications. Their high breakdown voltage and high switching frequency characteristics enable a drastic enhancement in power density and a significant reduction in complexity of the power electric system. However, proper power module packaging is critical to meet the sufficient insulation distance while simultaneously minimizing parasitics, especially at the module-system interface. This paper addresses the criticality effect of terminal arrangement on 10 kV power module performance. Three kinds of typical module layouts are compared in terms of system interface and parasitics. Thus, a concept of arranging terminals into groups according to the electric potential is proposed to provide a compact module layout with sufficient insulation. Based on this concept, an optimized terminal layout with low commutation loop inductance and attractive module-system interface is recommended for high voltage power module design.","PeriodicalId":127006,"journal":{"name":"2022 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"High Voltage SiC Power Module Optimized for Low Parasitics and Compatible System Interface\",\"authors\":\"Xiaoling Li, Yuxiang Chen, Yuheng Wu, Hao Chen, W. Weber, Adel Nasiri, R. Cuzner, Yue Zhao, A. Mantooth\",\"doi\":\"10.1109/APEC43599.2022.9773726\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are strong candidates to replace Si devices in high voltage applications. Their high breakdown voltage and high switching frequency characteristics enable a drastic enhancement in power density and a significant reduction in complexity of the power electric system. However, proper power module packaging is critical to meet the sufficient insulation distance while simultaneously minimizing parasitics, especially at the module-system interface. This paper addresses the criticality effect of terminal arrangement on 10 kV power module performance. Three kinds of typical module layouts are compared in terms of system interface and parasitics. Thus, a concept of arranging terminals into groups according to the electric potential is proposed to provide a compact module layout with sufficient insulation. Based on this concept, an optimized terminal layout with low commutation loop inductance and attractive module-system interface is recommended for high voltage power module design.\",\"PeriodicalId\":127006,\"journal\":{\"name\":\"2022 IEEE Applied Power Electronics Conference and Exposition (APEC)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-03-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Applied Power Electronics Conference and Exposition (APEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APEC43599.2022.9773726\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Applied Power Electronics Conference and Exposition (APEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APEC43599.2022.9773726","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Voltage SiC Power Module Optimized for Low Parasitics and Compatible System Interface
SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are strong candidates to replace Si devices in high voltage applications. Their high breakdown voltage and high switching frequency characteristics enable a drastic enhancement in power density and a significant reduction in complexity of the power electric system. However, proper power module packaging is critical to meet the sufficient insulation distance while simultaneously minimizing parasitics, especially at the module-system interface. This paper addresses the criticality effect of terminal arrangement on 10 kV power module performance. Three kinds of typical module layouts are compared in terms of system interface and parasitics. Thus, a concept of arranging terminals into groups according to the electric potential is proposed to provide a compact module layout with sufficient insulation. Based on this concept, an optimized terminal layout with low commutation loop inductance and attractive module-system interface is recommended for high voltage power module design.