基于环路的多ghz时钟网络互连建模与优化方法

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012758

Xuejue Huang, P. Restle, T. Bucelot, Yu Cao, T. King

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引用次数: 7

摘要

针对多ghz时钟网络设计，提出了一种高效的基于环路的互连建模方法。高频效应，包括电感和接近效应被捕获。通过与电磁模拟和Power4芯片上的测量数据进行比较，验证了结果。

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Loop-based interconnect modeling and optimization approach for multi-GHz clock network design

An efficient loop-based interconnect modeling methodology is proposed for multi-GHz clock network design. High frequency effects, including inductance and proximity effects are captured. The results are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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