Study on offset reduction method for a fully differential filter employing symmetrical floating impedance scaling circuits

In this paper, a method to reduce the offset voltage of a fully differential filter employing symmetry-type floating impedance scaling (SFIS) circuits with prevention of wasteful power consumption is proposed. The problem of the filter employing the conventional SFIS circuit and a common-mode rejection (CMR) circuit is that DC offset voltages are high. In order to reduce the offset voltages, much operating currents are necessary for high gain amplifier in the CMR circuit. The proposed solution is to reduce the offset voltage by unifying a common-mode feedback (CMFB) circuit and the SFIS circuit unlike an ordinary way that the CMFB is combined with an OTA or an OPamp. The validity of the proposed technique is examined by simulation. The offset voltage of the 1st-order fully differential active lowpass filter employing the proposed circuit is about 1.56mV. Comparing the current consumption of proposed and the conventional SFIS circuits, the proposed one is reduced by 35.5%.