FET结构中源漏金属屏蔽对漏漏电流的影响

K. A. Yusof, Nurul Izzati Mohammad Noh, S. H. Herman, A. Abdullah, M. Hussin, W. Abdullah
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引用次数: 0

摘要

研究了FET结构中源漏金属屏蔽对漏极漏电流的影响。采用MIMOS的标准工艺在晶圆上制备了FET结构。在FET结构源极和漏极处溅射厚度为400 nm的铝(Al)作为金属屏蔽层。采用Keithley 236电流电压源对四种不同的源漏金属屏蔽层进行了明暗两种条件下的测试。测量是在一个具有可控光强的暗箱中进行的。除了漏极漏电流的研究外,本研究还研究了各种源漏金属屏蔽层布局设计对FET结构的光效应。研究发现,带源漏金属屏蔽的布局设计漏电流较不带源漏金属屏蔽的布局设计低。然而,源漏金属屏蔽的各种布局设计并不能消除光的影响。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effect of source-drain metal shield in FET structure on drain leakage current
This study presents the effect of source-drain metal shield in FET structure on drain leakage current. The FET structure was fabricated on the wafer by using MIMOS's standard fabrication process. Aluminum (Al) was sputtered with thickness of 400 nm as metal shield layer at the source and drain area of FET structure. There are four different layout designs of source-drain metal shield that were tested by Keithley 236 current-voltage sourcing under light and dark conditions. The measurements were carried out in a dark box with controllable light intensity. Besides the drain leakage current investigation, this study also investigates the light effect of various layout designs with source-drain metal shield on FET structure. It was found that the layout design with source-drain metal shield has lower drain leakage current compared to the layout design without source-drain metal shield. However, the various layout design of source-drain metal shield cannot eliminate the light effect.
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