Optimization of access latency in DRAM

Modern digital systems, which involve high data computations, suffer from high memory access latency; thus, latency becomes a core issue in the performance enhancement of these advance digital machines. Different factors are behind the high latency of advance digital systems. Approaches like array binding and allocation, code rewriting, and others are adopted to reduce the overall latency of these systems. In this paper, we explore new dimensions to achieve maximum latency optimization in applications that involve extensive memory access. The proposed algorithm of idle/slack time management utilizes empty slots in memory access of different memory modules by appropriately activating upcoming commands in advance. The optimization of latency is further increased by incorporating the multi-way conflict resolution algorithm in second stage and followed by the use of advance dynamic buffers in third stage. Our successive three stages approach of adopting slack time management, multi-way partitioning using min-cut algorithm, and the use of advance dynamic buffers yields better results. Comparison of the experimental results with different benchmarks shows that our proposed technique optimizes the existing page-mode technique by 9%. Hence, adopting this proposed optimization strategy significantly reduces overall latency of modern digital systems.