A 16Gbps Real-Time BF-based LDPC Decoder for IEEE 802.3an Standard

Existing LDPC decoders are mostly based onbelief-propagation (BP) algorithms for high decodingperformance but demand high hardware cost, especially forapplications with very high throughputs. In order toalleviate the problem, this work proposes a high-throughputLDPC decoder based on the much simpler bit-flipping (BF)algorithms, for the (2048, 1723) RS-LDPC code adopted inthe IEEE 802.3an standard. High decoding performancesand low iteration numbers are achieved by introducing astrategy of flipping low-correlation bits and an additionalsyndrome vote scheme. As a result, the decodingperformance is comparable to the most popular BP-basedmin-sum algorithm (MSA) but with much lowercomputational complexity. Besides, the decoder achieveshigh hardware utilization with real-time processingcapability. Synthesized with UMC 90nm process, thedecoder chip area, throughput and average powerdissipation are 1.22M gates, 16Gbps and 315mW,respectively, at 500MHz clock rate.