一种4路VLIW嵌入式处理器及其配套芯片

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896984

Y. Hirose, M. Saito, Hiroyuki Utsumi, Toshiaki Saruwatari, A. Suga, T. Sukemura, H. Takahashi, H. Miyake, Y. Takebe, M. Kimura, H. Okano, Masayuki Tsuji, T. Satoh, T. Katayama

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引用次数: 0

摘要

基于改进的VLIW体系结构，开发了一种4路VLIW微处理器，用于0.18 /spl mu/m 5层金属CMOS工艺的嵌入式应用。该处理器配备了一个双向整数管道和一个双向浮动/媒体管道。每个浮动管道和介质管道分别具有2并行和4并行SIMD机制。处理器配备单独的指令和数据缓存;每个16 KB大小和4路集合相关联。6.7 M晶体管集成在7.5 mm/spl倍/7.5 mm的面积上。我们还开发了与处理器配套使用的配套芯片。配套芯片采用0.25 /spl μ m 4层金属CMOS工艺制造。

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A 4-way VLIW embedded processor and its companion chip

A 4-way VLIW microprocessor based on an improved VLIW architecture is developed for embedded application in a 0.18 /spl mu/m 5-layer-metal CMOS process. This processor equips a 2-way integer pipeline and a 2-way floating/media pipeline. Each floating pipeline and media pipeline has 2-parallel and 4-parallel SIMD mechanisms, respectively. The processor equips separate instruction and data caches; each of 16 KB size and 4-way set associative. 6.7 M transistors are integrated in an area of 7.5 mm/spl times/7.5 mm. We also developed companion chip which is used together with the processor. Companion chip is fabricated using a 0.25 /spl mu/m 4-layer-metal CMOS process.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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