模拟有源扩散区阵列类型和栅极几何形状对SiC S/D应力源窄型nmosfet的影响

2014 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2014-07-28 DOI:10.1109/INEC.2014.7460419

Chang-Chun Lee, C. Hsieh, M. Liao, Sen-Wen Cheng, Yu-Huan Guo

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引用次数: 0

摘要

在考虑源源/漏源嵌入式硅碳合金和拉伸接触蚀刻停止层(CESL)的高级应力源的情况下，为了研究虚拟有源扩散区(OD)和布局模式的凸极宽度对纳米器件迁移率增益的综合应变影响，本研究采用了一种经过验证的面向制造的应力模拟方法来估计22nm NMOSFET的性能。

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Effects of array type of dummy active diffused region and gate geometries on narrow NMOSFETs with SiC S/D stressors

To investigate the combined strained effects of dummy active diffused region (OD) and salient gate width of layout pattern on the mobility gain of nano-scaled device while advanced stressors of source/drain embedded silicon-carbon alloy and a tensile contact etch stop layers (CESL) are taken into account, the study uses a validated fabricated-oriented stress simulated methodology to estimate the performance of a 22nm NMOSFET.

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2014 IEEE International Nanoelectronics Conference (INEC)

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