CMOS image sensor with FPN reduction by correlated double sampling in current mode

The Active Pixel Sensor (APS) has been the preferred choice for CMOS image sensor topology in the last decades. However, due to process variations, parameter mismatches arise and lead to Fixed-Pattern Noise (FPN), which occurs across the APS array. A common technique to reduce FPN is the use of Correlated Double Sampling (CDS) in voltage mode to reduce the FPN, but it increases the complexity of either the pixel or the external circuitry. This paper, on the other hand, presents a CDS circuit operating in current mode to reduce FPN. The subtraction operation in current mode requires simpler circuitry, optimizing the trade-off between FPN reduction and the demand for silicon area. This technique does not require any topology change in the APS pixel itself or in its basic operation cycle. Simulations and experimental results show that the proposed technique can reduce the total FPN by more than 40%.