{"title":"CMOS技术达到规模极限后","authors":"H. Iwai","doi":"10.1109/IWJT.2008.4540004","DOIUrl":null,"url":null,"abstract":"Progress of CMOS LSI has been accomplished by the downsizing of MOSFETs. However, it has been expected that the downscaling will reach its limits about the gate length of 5 nm around the year of 2020. 2020 is not too far, but there is no sufficiently clear image for the world after CMOS reaches its scaling limit. This paper will discuss the picture of the CMOS technology in the world after the 2020.","PeriodicalId":369763,"journal":{"name":"Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"CMOS technology after reaching the scale limit\",\"authors\":\"H. Iwai\",\"doi\":\"10.1109/IWJT.2008.4540004\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Progress of CMOS LSI has been accomplished by the downsizing of MOSFETs. However, it has been expected that the downscaling will reach its limits about the gate length of 5 nm around the year of 2020. 2020 is not too far, but there is no sufficiently clear image for the world after CMOS reaches its scaling limit. This paper will discuss the picture of the CMOS technology in the world after the 2020.\",\"PeriodicalId\":369763,\"journal\":{\"name\":\"Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWJT.2008.4540004\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWJT.2008.4540004","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Progress of CMOS LSI has been accomplished by the downsizing of MOSFETs. However, it has been expected that the downscaling will reach its limits about the gate length of 5 nm around the year of 2020. 2020 is not too far, but there is no sufficiently clear image for the world after CMOS reaches its scaling limit. This paper will discuss the picture of the CMOS technology in the world after the 2020.