{"title":"用于监测由NBTI引起的频率衰减的片上电路","authors":"K. Stawiasz, K. Jenkins, P. Lu","doi":"10.1109/RELPHY.2008.4558941","DOIUrl":null,"url":null,"abstract":"This work describes the design and characterization of a unique circuit which can be easily integrated into a microprocessor product in order to determine the degradation of circuit speed caused by negative bias temperature instability (NBTI)-induced shifts under typical product operating voltage and temperature. These data can subsequently be compared to models for circuit degradation in order to assess the validity of the models.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"On-Chip circuit for monitoring frequency degradation due to NBTI\",\"authors\":\"K. Stawiasz, K. Jenkins, P. Lu\",\"doi\":\"10.1109/RELPHY.2008.4558941\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes the design and characterization of a unique circuit which can be easily integrated into a microprocessor product in order to determine the degradation of circuit speed caused by negative bias temperature instability (NBTI)-induced shifts under typical product operating voltage and temperature. These data can subsequently be compared to models for circuit degradation in order to assess the validity of the models.\",\"PeriodicalId\":187696,\"journal\":{\"name\":\"2008 IEEE International Reliability Physics Symposium\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.2008.4558941\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2008.4558941","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-Chip circuit for monitoring frequency degradation due to NBTI
This work describes the design and characterization of a unique circuit which can be easily integrated into a microprocessor product in order to determine the degradation of circuit speed caused by negative bias temperature instability (NBTI)-induced shifts under typical product operating voltage and temperature. These data can subsequently be compared to models for circuit degradation in order to assess the validity of the models.
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