{"title":"采用霍夫曼风格编码的低功耗FSM设计","authors":"P. Surti, L. Chao, A. Tyagi","doi":"10.1109/EDTC.1997.582410","DOIUrl":null,"url":null,"abstract":"This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"174 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"Low power FSM design using Huffman-style encoding\",\"authors\":\"P. Surti, L. Chao, A. Tyagi\",\"doi\":\"10.1109/EDTC.1997.582410\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively.\",\"PeriodicalId\":297301,\"journal\":{\"name\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"volume\":\"174 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-03-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1997.582410\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings European Design and Test Conference. ED & TC 97","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1997.582410","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively.