一种用于逆运动学位置计算的最大流水线CORDIC结构

C. S. Lee, P. Chang
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引用次数: 52

摘要

基于闭式关节方程的函数分解,提出了一种经济有效的坐标旋转数字计算机(CORDIC)结构。函数分解在计算流和数据依赖性中显示了有限的并行性和大量的顺序性,并揭示了计算大量初等运算的需求:乘法、加法、除法、平方根、三角函数及其反函数。然而,这些基本的操作,一般来说,不能有效地计算在通用的单处理器计算机。CORDIC算法是高效计算这些基本运算的自然候选算法,而这些CORDIC处理器之间的互连利用了流水线的巨大潜力,为计算运动学逆解提供了更好的解决方案。将运动学位置逆解的函数分解为一组计算任务,可以表示为有向任务图。输入数据的包含将任务图修改为非循环数据依赖图(ADDG)。ADDG的节点对应于计算模块,每个计算模块都可以通过CORDIC处理器来实现。操作数或数据沿着边缘移动,每个边缘连接一对节点。由于每个CORDIC处理器的路径和计算时间不同,操作数到达多输入模块的时间可能不同,导致流水线时间较长。可以在各种路径上插入延迟缓冲器,以实现平衡的ADDG。将缓冲区最优分配问题简化为一个整数线性优化问题,便于计算机求解。平衡式ADDG的实现使其能够以最少的延迟缓冲级实现最大流水线化的CORDIC结构,从而实现运动学位置逆解的计算。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A maximum pipelined CORDIC architecture for inverse kinematic position computation
A cost-effective coordinate rotation digital computer (CORDIC) architecture is described for the computation of inverse kinematic position solution based on a functional decomposition of the closed-form joint equations. The functional decomposition shows a limited amount of parallelism with a large amount of sequentialism in the flow of computation and data dependencies and reveals the requirement for computing a large set of elementary operations: multiplications, additions, divisions, square roots, trigonometric functions and their inverse. However, these elementary operations, in general, cannot be efficiently computed in general-purpose uniprocessor computers. The CORDIC algorithms are the natural candidates for efficiently computing these elementary operations and the interconnection of these CORDIC processors to exploit the great potential of pipelining provides a better solution for computing the inverse kinematic position solution. The functional decomposition of the inverse kinematic position solution into a set of computational tasks can be represented as a directed task graph. The inclusion of input data modifies the task graph to an acyclic data dependency graph (ADDG). The nodes of the ADDG correspond to the computational modules, each of which can be realized by a CORDIC processor. The operands or data move along the edges, each of which connects a pair of nodes. Due to different paths and computation time for each CORDIC processor, operands may arrive at multi-input modules at different arrival time, causing a longer pipelined time. Delay buffers may be inserted at various paths to achieve a balanced ADDG. The optimal buffer assignment problem is reduced to an integer linear optimization problem which can be solved easily by computers. The realization of the balanced ADDG results in a maximum pipelined CORDIC architecture with a minimum number of delay buffer stages for the computation of inverse kinematic position solution.
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