采用45纳米SOI CMOS的20-33 GHz直接转换发射机

Tiantong Ren, S. Hari, B. Floyd
{"title":"采用45纳米SOI CMOS的20-33 GHz直接转换发射机","authors":"Tiantong Ren, S. Hari, B. Floyd","doi":"10.1109/BCICTS48439.2020.9392967","DOIUrl":null,"url":null,"abstract":"This paper presents a 20–33 GHz direct-conversion transmitter implemented in 45-nm RFSOI CMOS technology. The transmitter features a divider-based quadrature clock generation circuit, two current-combined double-balanced mixers, and a balanced power amplifier (PA) employing stacked FETs. The transmitter chip achieves 19.1 to 22.4 dB of conversion gain with saturated output power of 16.7 to 20.4 dBm over 20 to 33 GHz at the differential output. Image rejection and carrier suppression are more than 29 dB and 36 dB after calibration. At a carrier frequency of 28 GHz, the transmitter chip achieves an error vector magnitude (EVM) of 5.1 % with 12 Gbps using 64-QAM.","PeriodicalId":355401,"journal":{"name":"2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"139-140 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 20-33 GHz Direct-Conversion Transmitter in 45-nm SOI CMOS\",\"authors\":\"Tiantong Ren, S. Hari, B. Floyd\",\"doi\":\"10.1109/BCICTS48439.2020.9392967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 20–33 GHz direct-conversion transmitter implemented in 45-nm RFSOI CMOS technology. The transmitter features a divider-based quadrature clock generation circuit, two current-combined double-balanced mixers, and a balanced power amplifier (PA) employing stacked FETs. The transmitter chip achieves 19.1 to 22.4 dB of conversion gain with saturated output power of 16.7 to 20.4 dBm over 20 to 33 GHz at the differential output. Image rejection and carrier suppression are more than 29 dB and 36 dB after calibration. At a carrier frequency of 28 GHz, the transmitter chip achieves an error vector magnitude (EVM) of 5.1 % with 12 Gbps using 64-QAM.\",\"PeriodicalId\":355401,\"journal\":{\"name\":\"2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"volume\":\"139-140 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-11-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BCICTS48439.2020.9392967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCICTS48439.2020.9392967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一种采用45纳米RFSOI CMOS技术实现的20-33 GHz直接转换发射机。该发射机具有一个基于分频器的正交时钟产生电路,两个电流组合双平衡混频器和一个采用堆叠场效应管的平衡功率放大器(PA)。在差分输出的20 ~ 33 GHz范围内,发射芯片的转换增益为19.1 ~ 22.4 dB,饱和输出功率为16.7 ~ 20.4 dBm。校正后的图像抑制和载波抑制分别大于29 dB和36 dB。在载波频率为28 GHz时,使用64-QAM的发射机芯片以12 Gbps的速度实现了5.1%的误差矢量幅度(EVM)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 20-33 GHz Direct-Conversion Transmitter in 45-nm SOI CMOS
This paper presents a 20–33 GHz direct-conversion transmitter implemented in 45-nm RFSOI CMOS technology. The transmitter features a divider-based quadrature clock generation circuit, two current-combined double-balanced mixers, and a balanced power amplifier (PA) employing stacked FETs. The transmitter chip achieves 19.1 to 22.4 dB of conversion gain with saturated output power of 16.7 to 20.4 dBm over 20 to 33 GHz at the differential output. Image rejection and carrier suppression are more than 29 dB and 36 dB after calibration. At a carrier frequency of 28 GHz, the transmitter chip achieves an error vector magnitude (EVM) of 5.1 % with 12 Gbps using 64-QAM.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信