将UVM_REG模型扩展到自动化和简单使用

A. Jain, Richa Gupta
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引用次数: 4

摘要

标准的UVM寄存器包包含内置的测试序列库,用于执行大多数基本的寄存器和内存测试。这些序列在IP级验证中非常有用,但在寄存器数量非常大的SoC级验证中,这些序列需要很长时间才能运行。类似地,目前用户需要强大的SV UVM语言知识来使用UVM_REG寄存器模型,验证环境代码对于不熟悉UVM的验证工程师/设计师来说似乎非常复杂。当前版本的UVM_REG包的一些限制,如没有内存访问的自动数据检查和内存突发操作的有限支持也被看到。在本文中,我们将描述如何解决上述问题。我们通过测试开发中使用的标准API(基于UVM_REG寄存器模型)访问处理器可编程寄存器和存储器。这个API旨在编写更简单的定向测试,不需要或更少地理解SV/UVM。该API可用于促进从IP到SoC重用的转储寄存器访问,或格式化输出以用于ATE测试向量开发等。在这些api中,提供了基本到更复杂的基于操作系统的功能。我们还开发了自己的寄存器/内存序列,以解决SoC级寄存器和内存测试。编写自定义代码以增强标准UVM_REG寄存器和内存模型的功能。还开发了基于IP-XACT的工具,用于自动生成使用标准寄存器模型所需的所有验证环境文件。集成了UVM_REG寄存器模型的验证环境用于验证物联网(IoT)等各种协议、应用和领域的各种设备。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Scaling the UVM_REG Model towards Automation and Simplicity of Use
The standard UVM register package contains built-in test sequences library which is used to perform most of the basic register and memory tests. These sequences are very useful at IP level verification but at SoC level verification where number of registers are very large, these sequences take very long time to run. Similarly, currently users require strong knowledge of SV UVM language to use UVM_REG register model and verification environment code seems to be very complex to verification engineers/designers which are not expert in UVM. Some limitations in current version of UVM_REG package like no automatic data checking for memory accesses and limited support for memory burst operation were also seen. In this paper, we are describing how we addressed the above mentioned issues. We are accessing processor programmable registers and memories through a standard API (based on UVM_REG register model) used in test development. This API is aimed at writing simpler directed tests which require less or no SV/UVM understanding. This API can be used to facilitate dumping register access for reuse from IP to SoC, or format outputs for use in ATE test vectors development etc. In these APIs, basic to more complex OS based capability is provided. We also developed our own register/memory sequences to address the SoC level register and memory testing. Customized code is written to enhance the features of standard UVM_REG Register and Memory Model. IP-XACT based tools are also developed to automatically generate all required verification environment files for using standard register model. Verification Environments with UVM_REG register model integrated are used to verify a variety of devices covering various protocols, applications and domains as the Internet of Things (IoT).
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