高速数字电子封装中功率/地平面噪声建模

Proceedings of IEEE Electrical Performance of Electronic Packaging Pub Date : 1993-10-20 DOI:10.1109/EPEP.1993.394553

J. Fang, Y. Liu, Y. Chen, Z. Wu, A. Agrawal

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引用次数: 37

摘要

提出了一种原理简单、求解准确、适用于各级高速数字电子封装的电源/地平面噪声仿真新模型。研究发现，无需采用全波电磁建模，就可以获得功率面和地面上的δ - 1噪声的精确建模。给出了用该方法模拟δ - 1噪声的示例结果。

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Modeling of power/ground plane noise in high speed digital electronics packaging

A new model for the simulation of power/ground plane noise which is simple in principle, accurate in its solutions, and applicable to various levels of high-speed digital electronics packaging, is given. It is found that one can obtain accurate modeling of delta-I noise in power and ground planes without resorting to full-wave electromagnetic modeling. Sample results of the simulated delta-I noise with the method are shown.<>

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Proceedings of IEEE Electrical Performance of Electronic Packaging

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