用于深亚微米SoC设计的多线程HDL模拟器

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI:10.1109/APCCAS.2004.1412695

T. Chan

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引用次数: 6

摘要

这项工作描述了一个多线程，64位，HDL(硬件描述语言)模拟器，V2Sim/spl贸易/，它可以显着加速先进的深亚微米片上系统(SoC)电路的设计验证，在任何商用对称多处理(SMP)计算机上提高10/spl倍或更多。这项工作介绍了V2Sim/spl trade/使用的专利多线程模拟算法，并将描述V2Sim/spl trade/的基准结果，以展示最先进算法的有效性。

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A multithreaded HDL simulator for deep submicron SoC designs

This work describes a multithreaded, 64-bit, HDL (hardware description language) simulator, V2Sim/spl trade/, which can significantly accelerate the design verification of advanced deep submicron system-on-chip (SoC) circuits by 10/spl times/ or more on any commercial symmetrical multiprocessing (SMP) computers. This work presents the patented, multithreaded simulation algorithm used by V2Sim/spl trade/, and benchmark results of V2Sim/spl trade/ will be depicted to demonstrate the effectiveness of the state-of-the-art algorithm.

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The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

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