G. Swift, S. Stone, S. E. García, Kevin W. Wray, W. Rowe, Krysten H. Pfau, Robert Liu, J. Holden, Asa Angeles, Barry L. Willits, Kyle P. Robinson, Andrés Pérez-Celis, M. Wirthlin
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Dynamic SEE Testing of Selected Architectural Features of Xilinx 28 nm Virtex-7 FPGAs
Recent proton and heavy ion SEE data are presented for selected Virtex-7 architectural features requiring dynamic in-beam testing: I/O blocks in various modes, IOSERDES, digital- and phase-locked loop clocks, and block memory’s error correction circuitry.