Xilinx 28纳米Virtex-7 fpga选定架构特征的动态SEE测试

G. Swift, S. Stone, S. E. García, Kevin W. Wray, W. Rowe, Krysten H. Pfau, Robert Liu, J. Holden, Asa Angeles, Barry L. Willits, Kyle P. Robinson, Andrés Pérez-Celis, M. Wirthlin
{"title":"Xilinx 28纳米Virtex-7 fpga选定架构特征的动态SEE测试","authors":"G. Swift, S. Stone, S. E. García, Kevin W. Wray, W. Rowe, Krysten H. Pfau, Robert Liu, J. Holden, Asa Angeles, Barry L. Willits, Kyle P. Robinson, Andrés Pérez-Celis, M. Wirthlin","doi":"10.1109/RADECS.2017.8696210","DOIUrl":null,"url":null,"abstract":"Recent proton and heavy ion SEE data are presented for selected Virtex-7 architectural features requiring dynamic in-beam testing: I/O blocks in various modes, IOSERDES, digital- and phase-locked loop clocks, and block memory’s error correction circuitry.","PeriodicalId":223580,"journal":{"name":"2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Dynamic SEE Testing of Selected Architectural Features of Xilinx 28 nm Virtex-7 FPGAs\",\"authors\":\"G. Swift, S. Stone, S. E. García, Kevin W. Wray, W. Rowe, Krysten H. Pfau, Robert Liu, J. Holden, Asa Angeles, Barry L. Willits, Kyle P. Robinson, Andrés Pérez-Celis, M. Wirthlin\",\"doi\":\"10.1109/RADECS.2017.8696210\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent proton and heavy ion SEE data are presented for selected Virtex-7 architectural features requiring dynamic in-beam testing: I/O blocks in various modes, IOSERDES, digital- and phase-locked loop clocks, and block memory’s error correction circuitry.\",\"PeriodicalId\":223580,\"journal\":{\"name\":\"2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RADECS.2017.8696210\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADECS.2017.8696210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

最近的质子和重离子SEE数据展示了需要动态束流内测试的Virtex-7架构特征:各种模式的I/O块,IOSERDES,数字和锁相环路时钟,以及块存储器的纠错电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Dynamic SEE Testing of Selected Architectural Features of Xilinx 28 nm Virtex-7 FPGAs
Recent proton and heavy ion SEE data are presented for selected Virtex-7 architectural features requiring dynamic in-beam testing: I/O blocks in various modes, IOSERDES, digital- and phase-locked loop clocks, and block memory’s error correction circuitry.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信