{"title":"Cadence 180nm 3-T Xor电池和8-T加法器设计综述","authors":"A. Khan, Shivendra Pandey, Jyotirmoy Pathak","doi":"10.1109/I2CT.2014.7092068","DOIUrl":null,"url":null,"abstract":"The paper gives a review of already existing 3-T XOR cells and provides an optimized value of (W/L) on the basis of simulation results obtained, so as to improve the threshold loss problems present in the existing designs of 3-T XOR cells thus helping improve the driving capability, however the driving capability is not sufficient for large circuits like multipliers, hence has a scope for further improvement. Using the best improved version of 3-T XOR cell a Full Adder Circuits is designed. All the basic circuits and their improved versions have been implemented in Cadence Virtuoso for 180nm technology and 1.8v sources.","PeriodicalId":384966,"journal":{"name":"International Conference for Convergence for Technology-2014","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A review paper on 3-T Xor cells and 8-T adder design in Cadence 180nm\",\"authors\":\"A. Khan, Shivendra Pandey, Jyotirmoy Pathak\",\"doi\":\"10.1109/I2CT.2014.7092068\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper gives a review of already existing 3-T XOR cells and provides an optimized value of (W/L) on the basis of simulation results obtained, so as to improve the threshold loss problems present in the existing designs of 3-T XOR cells thus helping improve the driving capability, however the driving capability is not sufficient for large circuits like multipliers, hence has a scope for further improvement. Using the best improved version of 3-T XOR cell a Full Adder Circuits is designed. All the basic circuits and their improved versions have been implemented in Cadence Virtuoso for 180nm technology and 1.8v sources.\",\"PeriodicalId\":384966,\"journal\":{\"name\":\"International Conference for Convergence for Technology-2014\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference for Convergence for Technology-2014\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/I2CT.2014.7092068\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference for Convergence for Technology-2014","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/I2CT.2014.7092068","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A review paper on 3-T Xor cells and 8-T adder design in Cadence 180nm
The paper gives a review of already existing 3-T XOR cells and provides an optimized value of (W/L) on the basis of simulation results obtained, so as to improve the threshold loss problems present in the existing designs of 3-T XOR cells thus helping improve the driving capability, however the driving capability is not sufficient for large circuits like multipliers, hence has a scope for further improvement. Using the best improved version of 3-T XOR cell a Full Adder Circuits is designed. All the basic circuits and their improved versions have been implemented in Cadence Virtuoso for 180nm technology and 1.8v sources.
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