a new type of high-performance low-power low clock-swing TSPC flip-flop

A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).