{"title":"体CMOS中寄生晶闸管的模型","authors":"W. D. Raburn","doi":"10.1109/IEDM.1980.189807","DOIUrl":null,"url":null,"abstract":"A model is presented for the parasitic SCR in bulk CMOS. The model shows the exact way that the shunting resistances alter the terminal V-I characteristics. It describes a negative differential resistance (NDR) range which is the only requirement for latch-up if certain biasing conditions are met. The NDR region will start when the product of current and shunting resistance equals the built in voltage and will occur for an+ ap< 1 (or βnβp< 1). The conditions for the center junction to become forward biased are given. If these conditions are met, the SCR will latch-up. If these conditions are not met, latch-up becomes dependent on the biasing circuit.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A model for the parasitic SCR in bulk CMOS\",\"authors\":\"W. D. Raburn\",\"doi\":\"10.1109/IEDM.1980.189807\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A model is presented for the parasitic SCR in bulk CMOS. The model shows the exact way that the shunting resistances alter the terminal V-I characteristics. It describes a negative differential resistance (NDR) range which is the only requirement for latch-up if certain biasing conditions are met. The NDR region will start when the product of current and shunting resistance equals the built in voltage and will occur for an+ ap< 1 (or βnβp< 1). The conditions for the center junction to become forward biased are given. If these conditions are met, the SCR will latch-up. If these conditions are not met, latch-up becomes dependent on the biasing circuit.\",\"PeriodicalId\":180541,\"journal\":{\"name\":\"1980 International Electron Devices Meeting\",\"volume\":\"112 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1980.189807\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A model is presented for the parasitic SCR in bulk CMOS. The model shows the exact way that the shunting resistances alter the terminal V-I characteristics. It describes a negative differential resistance (NDR) range which is the only requirement for latch-up if certain biasing conditions are met. The NDR region will start when the product of current and shunting resistance equals the built in voltage and will occur for an+ ap< 1 (or βnβp< 1). The conditions for the center junction to become forward biased are given. If these conditions are met, the SCR will latch-up. If these conditions are not met, latch-up becomes dependent on the biasing circuit.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
