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引用次数: 15
摘要
本文提出了一种新的SAR adc的DAC复位方案，消除了复位能耗。在低功率开关方案中，这种复位能耗可能是显著的，并且很少得到优化。该方案适用于所有差分复位和开关dac。这种“交换复位”操作应用于65nm CMOS制造的12b SAR ADC的2个msb，导致DAC节能33%或整个ADC节能18%。除交换外，还对DAC的2 msb进行旋转，以增强线性度至88dB SFDR。SAR ADC工作在0.8V VDD和40kS/s下，SNDR为64.2dB, FoM为7.1fJ/转换步长。
A 7.1fJ/conv.-step 88dB-SFDR 12b SAR ADC with energy-efficient swap-to-reset
In this work, a novel DAC reset scheme for SAR ADCs is proposed, which eliminates the reset energy consumption. This reset energy consumption can be significant and is seldom optimized in low power switching schemes. The scheme can be applied to all differentially reset and switched DACs. This `swap-to-reset' operation is applied to the 2 MSBs of a 12b SAR ADC fabricated in 65nm CMOS, resulting in an energy saving of 33% for the DAC or 18% for the whole ADC. Besides swapping, rotation is also applied to the 2 MSBs of the DAC to enhance the linearity to 88dB SFDR. The SAR ADC operates at 0.8V VDD and 40kS/s, achieving an SNDR of 64.2dB and a FoM of 7.1fJ/conversion-step.
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