{"title":"利用LDD结构的突触tft提高神经网络学习效率","authors":"Ryohei Morita, Y. Maeda, T. Matsuda, M. Kimura","doi":"10.1109/AM-FPD.2015.7173224","DOIUrl":null,"url":null,"abstract":"We are developing device-level neural networks using poly-Si TFTs. We succeeded in dramatically reducing the number of transistors in neurons and synapses to integrate a lot of devices, and we also succeeded in actually checking the operation of learning of logics. In this presentation, for the purpose of improvement of learning efficiency, we changed the synapse TFTs from the SD structure to the LDD structure. As a result, we succeeded in improving the learning efficiency by a 5×5 neural network.","PeriodicalId":243757,"journal":{"name":"2015 22nd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Improvement of learning efficiency in neural network using poly-Si TFTs by synapse TFTs with LDD structure\",\"authors\":\"Ryohei Morita, Y. Maeda, T. Matsuda, M. Kimura\",\"doi\":\"10.1109/AM-FPD.2015.7173224\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We are developing device-level neural networks using poly-Si TFTs. We succeeded in dramatically reducing the number of transistors in neurons and synapses to integrate a lot of devices, and we also succeeded in actually checking the operation of learning of logics. In this presentation, for the purpose of improvement of learning efficiency, we changed the synapse TFTs from the SD structure to the LDD structure. As a result, we succeeded in improving the learning efficiency by a 5×5 neural network.\",\"PeriodicalId\":243757,\"journal\":{\"name\":\"2015 22nd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)\",\"volume\":\"55 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 22nd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AM-FPD.2015.7173224\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 22nd International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AM-FPD.2015.7173224","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improvement of learning efficiency in neural network using poly-Si TFTs by synapse TFTs with LDD structure
We are developing device-level neural networks using poly-Si TFTs. We succeeded in dramatically reducing the number of transistors in neurons and synapses to integrate a lot of devices, and we also succeeded in actually checking the operation of learning of logics. In this presentation, for the purpose of improvement of learning efficiency, we changed the synapse TFTs from the SD structure to the LDD structure. As a result, we succeeded in improving the learning efficiency by a 5×5 neural network.