具有屏蔽栅和氧化沟槽的低米勒电容VDMOS

2016 IEEE International Nanoelectronics Conference (INEC) Pub Date : 2016-05-09 DOI:10.1109/INEC.2016.7589361

M. Ren, Zhe Chen, Bo Niu, Xiaofeng Cao, Shuangyue Li, Zehong Li, Bo Zhang

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引用次数: 4

摘要

提出了一种新的结构来提高VDMOS的米勒电容Cgd。该结构将传统VDMOS的栅极分为控制栅极和屏蔽栅极。此外，在屏蔽栅下的半导体表面引入了充满氧化物的沟槽。仿真结果表明，与传统结构相比，新结构的Cgd降低了31%，且几乎没有降低比导通电阻(Rsp, on)和击穿电压(BV)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A low miller capacitance VDMOS with shield gate and oxide trench

A novel structure was proposed to improve the Miller capacitance Cgd of VDMOS. The gate of conventional VDMOS is split into the control gate and the shield gate in the new structure. Moreover, a trench filled with oxide is introduced in the surface of semiconductor under the shield gate. According to the simulation, the new structure reduced Cgd by 31% compared with the conventional one, almost without degradation of the specific on-resistance (Rsp, on) and breakdown voltage (BV).

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2016 IEEE International Nanoelectronics Conference (INEC)

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