Yu-Hsuan Lin, Jau-Yi Wu, Ming-Hsiu Lee, Tien-Yen Wang, Yu-Yu Lin, F. Lee, Dai-Ying Lee, E. Lai, K. Chiang, H. Lung, K. Hsieh, T. Tseng, Chih-Yuan Lu
{"title":"采用智能写入算法对WOx ReRAM进行了优良的电阻变异性控制","authors":"Yu-Hsuan Lin, Jau-Yi Wu, Ming-Hsiu Lee, Tien-Yen Wang, Yu-Yu Lin, F. Lee, Dai-Ying Lee, E. Lai, K. Chiang, H. Lung, K. Hsieh, T. Tseng, Chih-Yuan Lu","doi":"10.1109/VLSI-TSA.2016.7480501","DOIUrl":null,"url":null,"abstract":"TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.","PeriodicalId":441941,"journal":{"name":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Excellent resistance variability control of WOx ReRAM by a smart writing algorithm\",\"authors\":\"Yu-Hsuan Lin, Jau-Yi Wu, Ming-Hsiu Lee, Tien-Yen Wang, Yu-Yu Lin, F. Lee, Dai-Ying Lee, E. Lai, K. Chiang, H. Lung, K. Hsieh, T. Tseng, Chih-Yuan Lu\",\"doi\":\"10.1109/VLSI-TSA.2016.7480501\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.\",\"PeriodicalId\":441941,\"journal\":{\"name\":\"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"volume\":\"171 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2016.7480501\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2016.7480501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Excellent resistance variability control of WOx ReRAM by a smart writing algorithm
TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.