W. Kuhn, C. Gilardi, D. Kirschner, J. Lang, S. Lange, Ming Liu, T. Perez, L. Schmitt, D. Jin, Lu Li, Zhen'An Liu, Yun-Ju Lu, Qiang Wang, Shujun Wei, Hao Xu, Dixin Zhao, K. Korcyl, J. Otwinowski, P. Salabura, I. Konorov, A. Mann
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FPGA - Based Compute Nodes for the PANDA Experiment at FAIR
PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10**7 /s and data rates of several 100 Gb Is. FPGA based compute nodes with multi-Gbit/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Each board is equipped with 5 Virtex4 FX60 FPGAs. High bandwidth connectivity is provided by four Gbit Ethernet links and 8 additional optical links connected to RocketIO ports. A single ATCA crate can host up to 14 boards which are interconnected via a full mesh backplane.
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