紧凑的12端口多银行寄存器文件测试芯片在0.35/spl μ m CMOS高度并行处理器

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI:10.1109/ASPDAC.2004.1337644

T. Sueyoshi, H. Uchida, H.J. Mattausch, T. Koide, Y. Mitani, T. Hironaka

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引用次数: 1

摘要

我们采用0.35μm CMOS技术，为高度并行处理器设计了一款紧凑、高速、低功耗的12端口寄存器文件测试芯片。在这种完全定制的测试芯片设计中，与传统的基于12端口单元的寄存器文件相比，面积缩小了72%，访问周期缩短了25%，功耗降低了62%。

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Compact 12-port multi-bank register file test-chip in 0.35/spl mu/m CMOS for highly parallel processors

We designed a compact, high-speed, and low-power hank-type 12-port register file test chip for highly-parallel processors in 0.35μm CMOS technology. In this full-custom test chip design, 72% smaller area, 25% shorter access cycle time, and 62% lower power consumption are achieved in comparison to the conventional 12-port-cell-based register file.

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ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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