Low-Power Frequency-Locked Loop Circuit with Static Frequency Offset Cancellation

A phase-locked loop (PLL) is an important and commonly used electronic circuit in various electronic systems. Its main drawback is the use of an RC low-pass filter which takes up the majority of the PLL area on the chip. The RC low-pass filter is necessary to ensure the PLL stability. To mitigate this issue, a frequency-locked loop (FLL) is used because the stability of an FLL system depends on the Miller capacitance inside of the operational amplifier, which drastically reduces the capacitor size and thus the chip area. This paper presents an improved design of a fully integrated FLL. It is based on a single frequency-to-voltage converter (FVC) which uses a single capacitor and a single charging current for the frequency-to-voltage conversion of both the input and output frequencies. The use of one FVC reduces the static frequency offset caused by the mismatch between the FVCs. The circuit is implemented in a 180-nm CMOS process. The measurements show that the new FLL design has increased precision and accuracy and similar chip area compared to the previous design. It has higher power consumption, increased delay time, overshoot and settling time, but they are comparable to those of the previous design.