Physical realization oriented area-power-delay tradeoff exploration

High level design-space exploration methodologies focus on optimizations on application and architectural abstraction layer. For power, leakage, and cost sensitive, as well as for performance critical SoC building blocks like embedded domain-specific processors and application specific accelerators, parasitic physical realization effects strongly influence the actual architecture efficiency. The tradeoff between architectural choices and physical implementation consequences needs to be considered to optimize area-power-performance efficiency. In this paper a semi-automated methodology is described that supports architectural optimizations with quantitative feedback on physical realizations already in an early design-space exploration phase. The presented methodology accounts for parasitic effects at the physical realization level, enables an efficient quantitative implementation tradeoff exploration for the design of high-performance SoC building blocks, and provides the foundation for a directed optimization throughout the design process.