Automating boundary scan design

ASIC and IC designers today are faced with the challenges of meeting strict design schedules and specifications, at the same time testability requirements are added. However, utilizing new top-down design techniques to automate the design, verification and testing of test logic such as IEEE 1149.1 boundary scan logic can be reduced from a six to eight week effort down to just days. This paper discusses a new technique of designing boundary scan in a top-down methodology, taking advantage of automated boundary-scan generation and automated logic synthesis.<>