RESURF nLDMOSFET in 0.351µm BiCMOS technology-characterization and modeling

In this paper, an nLDMOS transistor is developed by slight modifications of the base process steps of 0.35µm BiCMOS technology. Extra two masks are used for the formation of the body region (LB-PWELL) and the drift region with slightly added thermal budget and without resorting to high-tilt implants. The proposed device has a breakdown voltage independent of the epitaxial layer thickness. The specific ON-resistance (RON,SP) and the breakdown voltage (BV) are 1.5 mΩ.cm2 and 60V, respectively, so, the device can typically be operated around 42V supply voltage, which is suitable for the new automotive applications. The maximum drain current obtained at VGS of 3.3V is 0.42 mA/µm. A simple subcircuit model for the entire device is built using a two module approach, one for the intrinsic MOS area and the other for the drift region. The PSpice model parameters of the intrinsic MOS part are extracted using a system that links the ICCAP extraction tool with the results of the ISE-TCAD tools. The simulation results using the PSpice model are compared to the results provided by ISE-TCAD tools, and the accuracy at room temperature is less than 5% for the whole voltage domain.