{"title":"布斯无记忆模乘法器,有符号数字表示","authors":"Shuangching Chen, Shugang Wei, K. Shimizu","doi":"10.1109/APCCAS.2004.1412681","DOIUrl":null,"url":null,"abstract":"We present new Booth modular multipliers with a signed-digit number representation. The proposed Booth algorithm can recode the multiplier in which every two-digit has an element of the set {-2, -1, 0, 1, 2}. In a serial modular multiplier, the proposed Booth modular multipliers compared to earlier ones offer savings up 50 percent in the execution time. In a parallel multiplier, it can be up to 18.76 percent in the implementation area for modulus m = 255.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Booth memoryless modular multiplier with signed-digit number representation\",\"authors\":\"Shuangching Chen, Shugang Wei, K. Shimizu\",\"doi\":\"10.1109/APCCAS.2004.1412681\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present new Booth modular multipliers with a signed-digit number representation. The proposed Booth algorithm can recode the multiplier in which every two-digit has an element of the set {-2, -1, 0, 1, 2}. In a serial modular multiplier, the proposed Booth modular multipliers compared to earlier ones offer savings up 50 percent in the execution time. In a parallel multiplier, it can be up to 18.76 percent in the implementation area for modulus m = 255.\",\"PeriodicalId\":426683,\"journal\":{\"name\":\"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2004.1412681\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2004.1412681","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Booth memoryless modular multiplier with signed-digit number representation
We present new Booth modular multipliers with a signed-digit number representation. The proposed Booth algorithm can recode the multiplier in which every two-digit has an element of the set {-2, -1, 0, 1, 2}. In a serial modular multiplier, the proposed Booth modular multipliers compared to earlier ones offer savings up 50 percent in the execution time. In a parallel multiplier, it can be up to 18.76 percent in the implementation area for modulus m = 255.