Realization of Regula-Falsi Iteration based Double Precision Floating Point Division

One of the fundamental elements of modern microprocessor architectures is that they provide hardware support for arithmetic operations in floating point. In spite of the fact that division is a moderately rare operation in computer architecture, they are noteworthy and becoming progressively imperative in numerous modern applications. This paper presents design and implementation of Regula-Falsi (False Position) method for double precision floating point division. Floating point numbers are represented using IEEE 754 standard format. The presented algorithm iteratively computes reciprocal of 64-bit floating point divisor where two initial approximations are computed using ROM(s). The algorithm is implemented in Verilog Hardware Description Language (VHDL) and Zybo Zynq - 7000 Development FPGA Board is used to verify the same. For fairer comparison, the proposed method is compared with Newton Raphson counterpart, which is an existing algorithm that performs division operation iteratively. It has been proved that the proposed algorithm shows improvement in terms of number of number of iterations (computation cycles) and the accuracy of output.