一种分析和设计NWL方案DRAM的新方法

2008 IEEE International Reliability Physics Symposium Pub Date : 2008-07-09 DOI:10.1109/RELPHY.2008.4558996

Seokhan Park, Bonggu Sung, H. Jung, Junhee Lim, Sang-Woo Lee, Jooyoung Lee, Won-suk Yang, Kyungseok Oh, Taeyoung Chung, Kinam Kim

{"title":"一种分析和设计NWL方案DRAM的新方法","authors":"Seokhan Park, Bonggu Sung, H. Jung, Junhee Lim, Sang-Woo Lee, Jooyoung Lee, Won-suk Yang, Kyungseok Oh, Taeyoung Chung, Kinam Kim","doi":"10.1109/RELPHY.2008.4558996","DOIUrl":null,"url":null,"abstract":"One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor \"on\" current and to maintain \"off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A novel method to analyze and design a NWL scheme DRAM\",\"authors\":\"Seokhan Park, Bonggu Sung, H. Jung, Junhee Lim, Sang-Woo Lee, Jooyoung Lee, Won-suk Yang, Kyungseok Oh, Taeyoung Chung, Kinam Kim\",\"doi\":\"10.1109/RELPHY.2008.4558996\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor \\\"on\\\" current and to maintain \\\"off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.\",\"PeriodicalId\":187696,\"journal\":{\"name\":\"2008 IEEE International Reliability Physics Symposium\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.2008.4558996\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2008.4558996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

DRAM开发中最重要的问题之一是数据保留时间的控制。在存储单元设计中引入了负偏置的字线(NWL)关断电平，以改善单元晶体管的“导通”电流并保持足够低的“关断”电流。本文讨论了一种设计单元晶体管和NWL偏置电平的方法，以提高具有NWL的DRAM的数据保持时间。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A novel method to analyze and design a NWL scheme DRAM

One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2008 IEEE International Reliability Physics Symposium

自引率

0.00%

发文量