将高压器件添加到0.13/spl mu/m高电阻率薄SOI CMOS工艺中,用于混合模拟rf电路

O. Bon, L. Boissonnet, O. Gonnard, S. Chouteau, B. Reynard, A. Perrotin, C. Raynaud
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引用次数: 11

摘要

我们在0.13/spl mu/m薄SOI CMOS核心工艺中添加了具有高竞争力的SOI NLDEMOS,具有出色的功率开关和模拟特性。测量表明,漂移和BC设计规则都允许获得具有低S.Ron和低泄漏的HV器件(BV > 15V)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High voltage devices added to a 0.13/spl mu/m high resistivity thin SOI CMOS process for mixed analog-RF circuits
We have added to a 0.13/spl mu/m thin SOI CMOS core process a high competitive SOI NLDEMOS which presents excellent power switch and analog characteristics. Measurements have demonstrated that both drift and BC design rules allow to obtain HV devices (BV > 15V) with a low S.Ron and a low leakage.
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