{"title":"直接数字频率合成的分段抛物线插值","authors":"A. Eltawil, B. Daneshrad","doi":"10.1109/CICC.2002.1012856","DOIUrl":null,"url":null,"abstract":"In this paper, a compact architecture and implementation for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sinusoidal functions compared to existing architectures. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). The ROM size is consistently less than 1 Kbit for SFDR values up to 85 dBc.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Piece-wise parabolic interpolation for direct digital frequency synthesis\",\"authors\":\"A. Eltawil, B. Daneshrad\",\"doi\":\"10.1109/CICC.2002.1012856\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a compact architecture and implementation for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sinusoidal functions compared to existing architectures. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). The ROM size is consistently less than 1 Kbit for SFDR values up to 85 dBc.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"280 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012856\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012856","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Piece-wise parabolic interpolation for direct digital frequency synthesis
In this paper, a compact architecture and implementation for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sinusoidal functions compared to existing architectures. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). The ROM size is consistently less than 1 Kbit for SFDR values up to 85 dBc.