fpga上矩阵乘法的高能效架构

Kiran Kumar Matam, H. Le, V. Prasanna
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引用次数: 6

摘要

能源效率已成为关键绩效指标之一。在这项工作中,我们首先实现矩阵乘法的基线架构,参数化处理元素的数量和存储内存的类型。我们将这种架构映射到最先进的现场可编程门阵列(FPGA)上。生成一个设计空间来演示这些参数对能源效率的影响(定义为每焦耳的操作次数)。我们确定片上存储器构成了所有组件中最大的功耗。为了提高能量表现,我们提出了一个记忆激活计划。使用该方案,与最先进的矩阵乘法核心相比,所提出的优化设计在Energy×Area×Time (EAT)和能源效率方面分别提高了2.2倍和1.33倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Energy efficient architecture for matrix multiplication on FPGAs
Energy efficiency has emerged as one of the key performance metrics. In this work, we first implement a baseline architecture for matrix multiplication, parameterized with the number of processing elements and the types of storage memory. We map this architecture onto a state-of-the-art Field Programmable Gate Array (FPGA). A design space is generated to demonstrate the effect of these parameters on the energy efficiency (defined as number of operations per Joule). We determine that on-chip memory constitutes the largest amount of power consumption among all the components. To improve energy performance, we propose a memory activation schedule. Using this scheme, the proposed optimized design achieves 2.2x and 1.33x improvement with respect to Energy×Area×Time (EAT) and energy efficiency, respectively, compared with the state-of-the-art matrix multiplication core.
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