{"title":"容错WSI阵列处理器:伯杰码在并行算术逻辑单元中的使用","authors":"V. Piuri","doi":"10.1109/ICWSI.1990.63902","DOIUrl":null,"url":null,"abstract":"Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units\",\"authors\":\"V. Piuri\",\"doi\":\"10.1109/ICWSI.1990.63902\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation.<<ETX>>\",\"PeriodicalId\":206140,\"journal\":{\"name\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-01-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1990.63902\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 Proceedings. International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1990.63902","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units
Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation.<>
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