{"title":"MMU和缓存的共享标签","authors":"Yonghwan Lee, W. Jeong, Sangjun Ahn, Yongsurk Lee","doi":"10.1109/SMICND.1997.651553","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a shared tag memory through which both TLB and cache memory can be accessed. The shared tag architecture reduces the area of conventional cache tag memory and also improves the speed of cache system. To validate the proposed architecture, we conducted trace-driven simulations and measured the area and speed based on VLSI circuits.","PeriodicalId":144314,"journal":{"name":"1997 International Semiconductor Conference 20th Edition. CAS '97 Proceedings","volume":"21 10","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Shared tag for MMU and cache memory\",\"authors\":\"Yonghwan Lee, W. Jeong, Sangjun Ahn, Yongsurk Lee\",\"doi\":\"10.1109/SMICND.1997.651553\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a shared tag memory through which both TLB and cache memory can be accessed. The shared tag architecture reduces the area of conventional cache tag memory and also improves the speed of cache system. To validate the proposed architecture, we conducted trace-driven simulations and measured the area and speed based on VLSI circuits.\",\"PeriodicalId\":144314,\"journal\":{\"name\":\"1997 International Semiconductor Conference 20th Edition. CAS '97 Proceedings\",\"volume\":\"21 10\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 International Semiconductor Conference 20th Edition. CAS '97 Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMICND.1997.651553\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 International Semiconductor Conference 20th Edition. CAS '97 Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMICND.1997.651553","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we propose a shared tag memory through which both TLB and cache memory can be accessed. The shared tag architecture reduces the area of conventional cache tag memory and also improves the speed of cache system. To validate the proposed architecture, we conducted trace-driven simulations and measured the area and speed based on VLSI circuits.
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