Benjamin Viale, M. Fer, L. Courau, P. Galy, B. Jacquier, J. Lescot, B. Allard
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引用次数: 3
摘要
本文介绍了一种全芯片静电放电(ESD)验证工具——ESD IP Explorer。该工具的可行性首先在64引脚定制研发测试芯片上进行了验证。其可扩展性在第二个示例中进行了测试，该示例涉及138mm2 3,066个凸起原型，其基本验证在不到8小时的时间内完成。这两个例子都采用了28nm UTBB(超薄体和BOX -埋氧化物)FD-SOI高k金属栅极技术。最后讨论了更高级的静态验证特性。
An automated tool for chip-scale ESD network exploration and verification
This paper describes a tool for full-chip static ESD (ElectroStatic Discharge) verification called ESD IP Explorer. The tool feasibility is first demonstrated on a 64-pin custom R&D testchip. Its scalability is tested in a second example involving a 138mm2 3,066-bump prototype, which basic verification is performed in less than 8 hours. Both examples are in 28nm UTBB (Ultra-thin-body and BOX - Buried Oxide) FD-SOI High-K metal gate technology. More advanced static verification features are finally discussed.
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