Synchronous DRAM products evolutionize memory system design

Main memory devices, DRAMs, have traditionally quadrupled in size from one generation to the next with limited speed improvements. High speed SRAM caches have usually filled the bandwidth gap between MPU and DRAMs. Designers have recently realized that with the increased software complexity and MPU speed requirements, SRAM caches alone might not be able to provide the ultimate Performance/Cost solution. A new synchronous I/O structure has recently been developed for DRAMs (under the auspices of the joint electronic device engineering council, JEDEC) and set as the new standard for high performance devices called synchronous DRAMs.