性能驱动ECC电路合成的结构方法

C. Su, E. Chen, S. Jou
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引用次数: 1

摘要

ECCGen是一种用于错误控制编码电路的逻辑合成器。它将H矩阵作为输入,并分两个步骤生成电路原理图,文字最小化和门/引脚分配。与传统的逻辑综合工具不同,它采用结构化的方法来避免ECC电路的布尔函数和/或真表表示中的组合爆炸问题。此外,当使用多输入异或门时,该结构方法还显著降低了时序和面积优化的复杂性。测试结果表明,在13个工业ECC电路中,ECCGen实现了晶体管数量减少57%,延迟时间减少15%的效果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Structural approach for performance driven ECC circuit synthesis
ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization, and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the structural approach also reduce the complexity of timing and area optimization significantly when multiple-input exclusive-or gates are used. The test results show that ECCGen achieves a reduction of 57% in transistor count and 15% in delay time on thirteen industrial ECC circuits.
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