一种用于宽动态或门的时钟延迟睡眠模式多米诺逻辑

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. Pub Date : 2003-08-25 DOI:10.1145/871506.871550

Kwang-Il Oh, L. Kim

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引用次数: 19

摘要

提出了一种高性能、低功耗时钟延迟睡眠模式(CDSM)的宽扇入domino逻辑。CDSM-domino逻辑不仅提高了鲁棒性，而且降低了主动和待机功率。与0.18 /spl mu/m CMOS技术中典型的宽扇入多米诺逻辑相比，该方案分别降低了21%的延迟、16%的动态功率和91%的泄漏功率。此外，睡眠模式的入口功率降低到HS-domino逻辑的10/sup -5/。

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A clock delayed sleep mode domino logic for wide dynamic OR gate

A high performance and low power clock delayed sleep mode (CDSM) domino logic is proposed for wide fan-in domino logic. The CDSM-domino logic not only improves the robustness but also reduces the active and stand-by power. The proposed scheme reduces delay by 21%, dynamic power by 16%, and leakage power by 91% respectively compared to the typical wide fan-in domino logic in 0.18 /spl mu/m CMOS technology. In addition, the sleep mode entrance power is reduced to 10/sup -5/ of the HS-domino logic.

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来源期刊

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.

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