{"title":"基于优先级算法的大型集成电路测试技术","authors":"L. K. M. Ganesh, Lopamudra Pattanayak, K. Khare","doi":"10.1109/ICACT.2013.6710542","DOIUrl":null,"url":null,"abstract":"The paper presents a low test time BIST based on Priority Algorithm (PA) is applied for the 32-bit Carry Look-Ahead Adder. This method assigns priority to the test patterns based on faulty coverage and independent faulty detecting test patterns. Experiment conducted on Cadences' RTL Compiler Tool and Cadences' Encounter Tool demonstrate that proposed scheme gives better performance with large reduction in test time and power dissipation during testing.","PeriodicalId":302640,"journal":{"name":"2013 15th International Conference on Advanced Computing Technologies (ICACT)","volume":"206 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Priority algorithm based VLSI testing technique for BIST\",\"authors\":\"L. K. M. Ganesh, Lopamudra Pattanayak, K. Khare\",\"doi\":\"10.1109/ICACT.2013.6710542\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a low test time BIST based on Priority Algorithm (PA) is applied for the 32-bit Carry Look-Ahead Adder. This method assigns priority to the test patterns based on faulty coverage and independent faulty detecting test patterns. Experiment conducted on Cadences' RTL Compiler Tool and Cadences' Encounter Tool demonstrate that proposed scheme gives better performance with large reduction in test time and power dissipation during testing.\",\"PeriodicalId\":302640,\"journal\":{\"name\":\"2013 15th International Conference on Advanced Computing Technologies (ICACT)\",\"volume\":\"206 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 15th International Conference on Advanced Computing Technologies (ICACT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICACT.2013.6710542\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 15th International Conference on Advanced Computing Technologies (ICACT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICACT.2013.6710542","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Priority algorithm based VLSI testing technique for BIST
The paper presents a low test time BIST based on Priority Algorithm (PA) is applied for the 32-bit Carry Look-Ahead Adder. This method assigns priority to the test patterns based on faulty coverage and independent faulty detecting test patterns. Experiment conducted on Cadences' RTL Compiler Tool and Cadences' Encounter Tool demonstrate that proposed scheme gives better performance with large reduction in test time and power dissipation during testing.
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