{"title":"Z2-FET:在图像传感和自对准结构中的应用","authors":"J. Liu, J. Wan","doi":"10.23919/IWJT.2019.8802620","DOIUrl":null,"url":null,"abstract":"Zero impact ionization and zero subthreshold swing FET (Z 2 -FET) based on fully depleted silicon-on-insulator (FD-SOI) substrate is a novel device operating with the positive feedback mechanism between the flow of electrons and holes. It has been showing extremely sharp-switching property with SS down to 1mV/dec and ON/OFF ratio up to 10 8 [1] , [2] . Besides, the Z 2 -FET has a large hysteresis window from its I D −V D characteristics and the turn-on voltage (V ON ) linearly controlled by the gate voltage (V G ). This property has been utilized for one-transistor dynamic random access memory (DRAM) application, which has higher access speed and higher integration density compared to conventional one-transistor and one capacitor (1T-1C) DRAM [3] , [4] . However, conventional Z 2 -FET has an asymmetrical structure with a long channel region uncovered by the top gate. This asymmetrical structure not only causes increase of feature size, but also brings mis-alignment which can degrade the device performances.","PeriodicalId":441279,"journal":{"name":"2019 19th International Workshop on Junction Technology (IWJT)","volume":"66 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Z2-FET: Application in Image Sensing and Self-aligned Structure for Further Scaling Down\",\"authors\":\"J. Liu, J. Wan\",\"doi\":\"10.23919/IWJT.2019.8802620\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Zero impact ionization and zero subthreshold swing FET (Z 2 -FET) based on fully depleted silicon-on-insulator (FD-SOI) substrate is a novel device operating with the positive feedback mechanism between the flow of electrons and holes. It has been showing extremely sharp-switching property with SS down to 1mV/dec and ON/OFF ratio up to 10 8 [1] , [2] . Besides, the Z 2 -FET has a large hysteresis window from its I D −V D characteristics and the turn-on voltage (V ON ) linearly controlled by the gate voltage (V G ). This property has been utilized for one-transistor dynamic random access memory (DRAM) application, which has higher access speed and higher integration density compared to conventional one-transistor and one capacitor (1T-1C) DRAM [3] , [4] . However, conventional Z 2 -FET has an asymmetrical structure with a long channel region uncovered by the top gate. This asymmetrical structure not only causes increase of feature size, but also brings mis-alignment which can degrade the device performances.\",\"PeriodicalId\":441279,\"journal\":{\"name\":\"2019 19th International Workshop on Junction Technology (IWJT)\",\"volume\":\"66 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 19th International Workshop on Junction Technology (IWJT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/IWJT.2019.8802620\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 19th International Workshop on Junction Technology (IWJT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/IWJT.2019.8802620","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
基于完全耗尽绝缘体上硅(FD-SOI)衬底的零冲击电离零亚阈值摆幅场效应管(z2 -FET)是一种电子与空穴流动正反馈机制的新型器件。它已经显示出非常锐利的开关特性,SS低至1mV/dec,开/关比高达10.8[1],[2]。此外,z2 -FET的I - D - V - D特性和导通电压(V ON)由栅极电压(V G)线性控制,具有较大的滞后窗。这一特性已被用于单晶体管动态随机存取存储器(DRAM)应用,与传统的单晶体管一电容(1T-1C) DRAM相比,它具有更高的存取速度和更高的集成密度[3],[4]。然而,传统的z2 -FET具有不对称结构,顶部栅极覆盖了长沟道区域。这种不对称结构不仅会导致特征尺寸的增加,而且会带来不对准,从而降低器件的性能。
Z2-FET: Application in Image Sensing and Self-aligned Structure for Further Scaling Down
Zero impact ionization and zero subthreshold swing FET (Z 2 -FET) based on fully depleted silicon-on-insulator (FD-SOI) substrate is a novel device operating with the positive feedback mechanism between the flow of electrons and holes. It has been showing extremely sharp-switching property with SS down to 1mV/dec and ON/OFF ratio up to 10 8 [1] , [2] . Besides, the Z 2 -FET has a large hysteresis window from its I D −V D characteristics and the turn-on voltage (V ON ) linearly controlled by the gate voltage (V G ). This property has been utilized for one-transistor dynamic random access memory (DRAM) application, which has higher access speed and higher integration density compared to conventional one-transistor and one capacitor (1T-1C) DRAM [3] , [4] . However, conventional Z 2 -FET has an asymmetrical structure with a long channel region uncovered by the top gate. This asymmetrical structure not only causes increase of feature size, but also brings mis-alignment which can degrade the device performances.