{"title":"MOS源耦合对的线性化","authors":"Shicai Qin, Mu-Zhon Shao, Xiangluan Jia","doi":"10.1109/ICSICT.1995.499645","DOIUrl":null,"url":null,"abstract":"This paper presents a new linearization approach for a MOS source-coupled pair that utilizes a current I/sub ss/=a+bV/sup 2/ produced by an asymmetrical source-coupled pair as the tail current to cancel out its inherent nonlinearity. Simulation results show that under /spl plusmn/5 V bias voltage and over /spl plusmn/3 V input signal swings, the maximum full scale nonlinear error is /spl plusmn/0.68%.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The linearization of MOS source-coupled pair\",\"authors\":\"Shicai Qin, Mu-Zhon Shao, Xiangluan Jia\",\"doi\":\"10.1109/ICSICT.1995.499645\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new linearization approach for a MOS source-coupled pair that utilizes a current I/sub ss/=a+bV/sup 2/ produced by an asymmetrical source-coupled pair as the tail current to cancel out its inherent nonlinearity. Simulation results show that under /spl plusmn/5 V bias voltage and over /spl plusmn/3 V input signal swings, the maximum full scale nonlinear error is /spl plusmn/0.68%.\",\"PeriodicalId\":286176,\"journal\":{\"name\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1995.499645\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th International Conference on Solid-State and IC Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1995.499645","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a new linearization approach for a MOS source-coupled pair that utilizes a current I/sub ss/=a+bV/sup 2/ produced by an asymmetrical source-coupled pair as the tail current to cancel out its inherent nonlinearity. Simulation results show that under /spl plusmn/5 V bias voltage and over /spl plusmn/3 V input signal swings, the maximum full scale nonlinear error is /spl plusmn/0.68%.
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