{"title":"新的4.3 ppm//spl度/C基准电压，采用标准CMOS工艺，电源电压为1V","authors":"Q. X. Zhang, L. Siek","doi":"10.1109/ISCAS.2005.1465569","DOIUrl":null,"url":null,"abstract":"A new 1 V supply voltage reference, using a standard CMOS process, with threshold voltage close to the supply voltage is proposed. The threshold voltages of NMOS and PMOS are 0.81 V and -1.05 V respectively at a temperature of -25/spl deg/C. Simulation results show that the proposed design can achieve below 4.3 ppm//spl deg/C between -25/spl deg/C and 150/spl deg/C at supply voltage of 1 V; as the supply voltage increases to 2 V, the temperature coefficient only increases to 9.3 ppm//spl deg/C.","PeriodicalId":191200,"journal":{"name":"2005 IEEE International Symposium on Circuits and Systems","volume":"139 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A new 4.3 ppm//spl deg/C voltage reference using standard CMOS process with 1V supply voltage\",\"authors\":\"Q. X. Zhang, L. Siek\",\"doi\":\"10.1109/ISCAS.2005.1465569\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new 1 V supply voltage reference, using a standard CMOS process, with threshold voltage close to the supply voltage is proposed. The threshold voltages of NMOS and PMOS are 0.81 V and -1.05 V respectively at a temperature of -25/spl deg/C. Simulation results show that the proposed design can achieve below 4.3 ppm//spl deg/C between -25/spl deg/C and 150/spl deg/C at supply voltage of 1 V; as the supply voltage increases to 2 V, the temperature coefficient only increases to 9.3 ppm//spl deg/C.\",\"PeriodicalId\":191200,\"journal\":{\"name\":\"2005 IEEE International Symposium on Circuits and Systems\",\"volume\":\"139 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2005.1465569\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2005.1465569","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new 4.3 ppm//spl deg/C voltage reference using standard CMOS process with 1V supply voltage
A new 1 V supply voltage reference, using a standard CMOS process, with threshold voltage close to the supply voltage is proposed. The threshold voltages of NMOS and PMOS are 0.81 V and -1.05 V respectively at a temperature of -25/spl deg/C. Simulation results show that the proposed design can achieve below 4.3 ppm//spl deg/C between -25/spl deg/C and 150/spl deg/C at supply voltage of 1 V; as the supply voltage increases to 2 V, the temperature coefficient only increases to 9.3 ppm//spl deg/C.
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