分栅闪存单元阵列中擦除电压变异性的来源

2016 IEEE International Integrated Reliability Workshop (IIRW) Pub Date : 1900-01-01 DOI:10.1109/IIRW.2016.7904890

Y. Tkachev, J. Walls

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引用次数: 2

摘要

我们进行了一个全面的分析电压擦除(Verase)分布在分裂门闪存单元阵列。结果表明，Verase分布主要由隧穿电压的变化决定。其他因素，如耦合比分布和FG通道参数，对Verase变异的影响较小。

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The sources of erase voltage variability in split-gate flash memory cell arrays

We performed a comprehensive analysis of the voltage-to-erase (Verase) distribution in split-gate flash memory cell arrays. It was shown that Verase distribution is mostly determined by the tunneling voltage variations. Other factors, such as distributions of coupling ratio and FG channel parameters, have a minor effect on Verase variability.

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2016 IEEE International Integrated Reliability Workshop (IIRW)

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