{"title":"一种用于DS-UWB系统的模拟基带链","authors":"T. Koivisto, J. Maunu, E. Tiiliharju","doi":"10.1109/RME.2008.4595765","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a mixed-mode baseband chain using a high-speed analog Viterbi decoder. The circuit system architecture is presented with a link budget calculations and the baseband circuitry is introduced. Our target performance is 125 Mbit/s and 1 GbWs throughput at the distances of 10 and 1 m using a 1 GHz bandwidth dedicated to UWB systems between 3.1-4.9 GHz utilizing the analog Viterbi decoder. Proposed analog receiver architecture makes possible high-speed communication with decreased power consumption.","PeriodicalId":140550,"journal":{"name":"2008 Ph.D. Research in Microelectronics and Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An analog baseband chain for DS-UWB system\",\"authors\":\"T. Koivisto, J. Maunu, E. Tiiliharju\",\"doi\":\"10.1109/RME.2008.4595765\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a mixed-mode baseband chain using a high-speed analog Viterbi decoder. The circuit system architecture is presented with a link budget calculations and the baseband circuitry is introduced. Our target performance is 125 Mbit/s and 1 GbWs throughput at the distances of 10 and 1 m using a 1 GHz bandwidth dedicated to UWB systems between 3.1-4.9 GHz utilizing the analog Viterbi decoder. Proposed analog receiver architecture makes possible high-speed communication with decreased power consumption.\",\"PeriodicalId\":140550,\"journal\":{\"name\":\"2008 Ph.D. Research in Microelectronics and Electronics\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-08-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 Ph.D. Research in Microelectronics and Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RME.2008.4595765\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Ph.D. Research in Microelectronics and Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2008.4595765","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we propose a mixed-mode baseband chain using a high-speed analog Viterbi decoder. The circuit system architecture is presented with a link budget calculations and the baseband circuitry is introduced. Our target performance is 125 Mbit/s and 1 GbWs throughput at the distances of 10 and 1 m using a 1 GHz bandwidth dedicated to UWB systems between 3.1-4.9 GHz utilizing the analog Viterbi decoder. Proposed analog receiver architecture makes possible high-speed communication with decreased power consumption.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
